The present application generally relates to a parallel computing system. More particularly, the present application relates to a cache coherence protocol operated in the parallel computing system.
A traditional parallel computing system does not allow updates to the same cache line address by more than one thread(s) or processor(s) at a time. In other words, if a processor wants to update a cache line in an associated local cache memory device, the traditional parallel computing system must first invalidate the corresponding cache lines in other local cache memory devices. Cache coherent mechanisms are therefore implemented in computing systems to update local cache memory devices, e.g., to invalidate cache lines in local cache memory devices. Therefore, two or more distinct threads and/or processors in the traditional parallel computing system cannot simultaneously update the same cache line address running a cache coherence operation across local cache memory devices. To prevent the simultaneous updates of the same cache line address when accessed by two or more distinct thread(s) or processor(s), the traditional parallel computing system requires more frequent communications (e.g., broadcasting an invalidation notice to other local cache memory devices) between local cache memory devices, and frequently invalidates cache lines in local cache memory devices.